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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:30:32 03/10/2012 
-- Design Name: 
-- Module Name:    DataMemory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DataMemory is
    Port ( data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           data_addr_i : in  STD_LOGIC_VECTOR (7 downto 0);
           rw : in  STD_LOGIC;
           data_cyc_i : in  STD_LOGIC;
           data_stb_i : in  STD_LOGIC;
           data_ack_o : out  STD_LOGIC;
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
end DataMemory;

architecture Behavioral of DataMemory is
begin
	process(data_word_i, data_addr_i, rw, data_cyc_i, data_stb_i) is
		type ramtype is array (255 downto 0) of STD_LOGIC_VECTOR (7 downto 0); -- Con addr de 8 bit hay max 256 posiciones
		variable mem : ramtype := ((others => (others => '0'))); -- instancia la mem como una variable y la inicializa a 0
	begin
	
		if(data_cyc_i = '1' and data_stb_i = '1') then -- Si el ciclo de lectura/escritura es valido
			if(rw = '0') then 								  		-- Si estamos en LECTURA
				data_word_o <= mem(CONV_INTEGER(data_addr_i));
				data_ack_o <= '1';
			else													  		-- Si estamos en ESCRITURA
				mem(CONV_INTEGER(data_addr_i)) := data_word_i;
				data_ack_o <= '1';
			end if;
		else														  -- Si el ciclo de lectura/escritura no es valido
			data_ack_o <= '0';
		end if;
	
	end process;
end Behavioral;

